PLDA� Announces Robust Verification Toolset, Increasing Design Accuracy And Reducing Time-to-production for Next Generation SoCs With CXL�, PCIe� 6.0 or Gen-Z� Interconnect

Toolset includes components from PLDA’s own verification process as well as tools from industry-leading companies Aldec® , Avery Design Systems® and Mentor, a Siemens Business.

SAN JOSE, Calif.–(BUSINESS WIRE)–PLDA, the industry leader in PCI Express® IP and data interconnect solutions, today announced the Robust Verification Toolset, a breakthrough approach to IP verification dramatically increasing Design accuracy and speeding-up the time-to-market. The verification process for IP design takes place at the front end of chip design and requires a high level of reliability to prevent production delays. Achieving the necessary levels of verification can be time-consuming, however cutting corners in verification often results in costly and difficult bug fixes at the end of chip fabrication. It is much more efficient to ensure a robust and high-quality initial verification process. PLDA has built such a robust verification process, which combines a comprehensive tool set provided by leading external verification suppliers and augmented by PLDA’s own internal tools that can significantly increase time-to-design while improving design accuracy.

By using a rich ecosystem of best-in-class verification solutions, PLDA’s verification toolset enables careful and systematic analysis and substantiation showing that the design implementation will work for all possible defined behaviors. Behind PLDA’s innovative verification method is a proprietary PLDA tool called DANA that is used to deliver highly efficient supply chain management through a collection of automatic reports, automations, and strict follow-up processes. Data from the complete Toolset is automatically collected, analyzed, and reported, reducing review cycles caused by data management, and accelerating the decision process. This verification procedure, internally named “Supersprint”, is raising the level of flexibility to adapt to customer schedules and custom features while staying focused on the main R&D roadmap.

This Robust Verification Toolset is the result of a collaboration between PLDA, Aldec, Avery Design Systems and Mentor – all leading providers of verification products. It includes:

• Verification IPs covering standards compliance for PCIe, AMBA AXI, CXL, CCIX and Gen-Z
• Simulators that support mixed-language designs with UVM testbenches
• Synthesis and static verification tools from classic EDA providers, delivering verification of quality of RTL design and of CDC

According to Arnaud Schleich, CEO of PLDA “PLDA has long been a leader in producing highly respected and trusted IP designs, largely because of our commitment to strong verification. The creation of this toolset underscores not only our commitment to complete verification, but also to enabling flexibility of choice for our customers, as well as limited risks for their SoC production.”

“Mentor is pleased to enable our partner PLDA with the high performance Questa Verification IP (QVIP) solution for PCIe and AXI interconnect, and the Questa Simulation flow”, said Neil Hand, Director of Marketing in Mentor’s IC Verification Solutions division. “PLDA chose Questa Verification IP to provide PCIe standard compliance testing in their test suite, on a highly scalable and high performance testbench. The results of our collaboration will benefit mutual customers seeking a proven solution for PCIe in advanced designs.”

According to Chris Browy, VP Sales/Marketing from Avery Design Systems, “We have long been a PLDA partner, providing the robust verification solution including models and compliance testsuites needed for their many PCIe configurations including Endpoint, Root port, and Switch at speeds of up to PCIe 5.0. We are also a key collaborator on CXL and Gen-Z IP verification and are happy to be part of PLDA’s newest verification toolset, helping to deliver better and faster verification to our mutual customers.”

Louie De Luna, Director of Marketing from Aldec, said “PLDA employs Aldec’s Riviera-PRO™ for RTL simulation and debugging with UVM testbenches, which improves verification productivity in environments crucial for SoC and FPGA design. This is important for PLDA’s complete suite of interface IP and we are proud to be a partner of PLDA and to help enable a faster time-to-design.”

More information:

For more information about PLDA’s Verification Solutions:

• Review the technical article from Mentor and PLDA: “PCIe Simulation Speed-Up Using Mentor QVIP with PLDA PCIe Controller for DMA applications” at DAC 2020.
• Don’t miss the Aldec PCIe 5.0 Simulation/Verification demonstration in partnership with both PLDA and Avery at DAC 2020
• For more information about PLDA’s verification process, please visit www.plda.com

About PLDA

PLDA is a developer and licensor of Semiconductor Intellectual Property (SIP) specializing in high-speed interconnect supporting multi-gigabit rates (2.5G, 5G, 8G, 16G, 25G, 32G, 56G, 112G), and protocols such as PCI Express, CCIX, CXL, and Gen-Z. PLDA has established itself as a leader in that space with over 3,200 customers and 6,400 licenses in 62 countries. PLDA is a global technology company with offices in Silicon Valley, France, Bulgaria, Taiwan, and China.

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Trademarks

All registered trademarks and other trademarks belong to their respective owners. PCI-SIG, PCI Express and PCIe are trademarks or registered trademarks of PCI-SIG. Gen-Z is a trademark of the Gen-Z Consortium. CXL and Compute Express Links are trademarks of the Compute Express Link Consortium. XpressLINK is a trademark of PLDA.

Note: A list of relevant Siemens trademarks can be found here.

Contacts

PLDA
Romain Tourneau, Marketing Manager, +33 4 28 38 04 66, rtourneau@plda.com